View VND5050AJTR-E_570625.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VND5050AJ-E VND5050AK-E
Double channel high side driver with analog current sense for automotive applications
Features
General
Max supply voltage Operating voltage range Max On-State resistance (per ch.) Current limitation (typ) Off state supply current
(*) Typical value with all loads connected
VCC VCC RON ILIMH IS
41V 4.5 to 36V 50 m 18 A 2 A(*)

PowerSSO-12
PowerSSO-24
Self limiting of fast thermal transients Protection against loss of ground and loss of VCC Thermal shut down Reverse battery protection (see Figure 24) Electrostatic discharge protection
Application

All types of resistive, inductive and capacitive loads Suitable as LED driver
Main

Description
The VND5050AJ-E, VND5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears..
Inrush current active management by power limitation Very low stand-by current 3.0V CMOS compatible input Optimized electromagnetic emission Very low electromagnetic susceptibility In compliance with the 2002/95/ec european directive
Diagnostic Functions

Proportional load current sense High current sense precision for wide range currents Current sense disable Thermal shutdown indication Very low current sense leakage
Protections

Undervoltage shut-down Overvoltage clamp Load current limitation
Order codes
Package PowerSSO-12 PowerSSO-24 Part number (Tube) VND5050AJ-E VND5050AK-E Part number (Tape & Reel) VND5050AJTR-E VND5050AKTR-E
April 2006
Rev 2
1/26
www.st.com 26
Contents
VND5050AJ-E / VND5050AK-E
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 15
3.1.1 3.1.2 Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 3.3
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
VND5050AJ-E / VND5050AK-E
Block diagram and pin description
1
Figure 1.
Block diagram and pin description
Block Diagram
VCC
VCC CLAMP GND INPUT1 LOGIC
UNDERVOLTAGE OUTPUT1 PwCLAMP 1 DRIVER 1 ILIM 1 PwrLIM 1 VDSLIM 1 OVERTEMP. 1 DRIVER 2 ILIM 2 VDSLIM 2 OVERTEMP. 2 IOUT2 PwrLIM 2 K2 PwCLAMP 2 OUTPUT2 CURRENT SENSE2 CURRENT SENSE1
INPUT2
IOUT1 K1
CS_DIS
Table 1.
Name VCC
Pin Function
Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Analog current sense pin, delivers a current proportional to the load current Active high CMOS compatible pin, to disable the current sense pin
OUTPUT1,2 GND INPUT1,2 CURRENT SENSE1,2 CS_DIS
Figure 2.
Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = Vcc GND INPUT2 INPUT1 CURRENT SENSE1 CURRENT SENSE2 CS_DIS 1 2 3 4 5 6 12 11 10 9 8 7 Vcc OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 Vcc
VCC GND N.C. INPUT2 N.C. INPUT1 N.C. CURRENT SENSE1 N.C. CURRENT SENSE2 CS_DIS. VCC
OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1
TAB = VCC
PowerSSO-12 Connection / Pin Floating To Ground Current Sense N.R. Through 1K resistor N.C. X X Output X N.R.
PowerSSO-24 Input X Through 10K resistor CS_DIS X 10K
N.R. = Not recommended
3/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
2
Electrical specifications
Figure 3. Current and Voltage Conventions
IS VCC ICSD VCSD IIN1 VIN1 IIN2 VIN2 INPUT2 GND CURRENT SENSE2 ISENSE2 VSENSE2 INPUT1 CS_DIS IOUT1 VOUT1 ISENSE1 VSENSE1 IOUT2 VOUT2 VCC
OUTPUT1 CURRENT SENSE1 OUTPUT2
IGND
VFn = VOUTn - VCC during reverse battery condition
2.1
Absolute Maximum Ratings
Table 2.
Symbol VCC -VCC -IGND IOUT -IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current
Absolute Maximum Ratings
Parameter Value 41 0.3 200 Internally limited 12 -1 to 10 -1 to 10 200 VCC-41 +VCC 51 Unit V V mA A A mA mA mA V V mJ
-ICSENSE DC Reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (L=1.5mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) ) Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature
VESD
4000 2000 4000 5000 5000 750 -40 to 150 -55 to 150
V V V V V V C C
VESD Tj Tstg
4/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
2.2
Table 3.
Symbol
Thermal Data
Thermal Data
Value Parameter PowerSSO-12 PowerSSO-24 2.7 See Figure 30 C/W C/W Thermal resistance junction-case (Max.) (with one channel ON) Thermal resistance junction-ambient (Max.) Unit
Rthj-case Rthj-amb
2.7 See Figure 26
2.3
Table 4.
Symbol VCC VUSD VUSDhyst
Electrical Characteristics
8VPower section Parameter Operating supply voltage Undervoltage shutdown Undervoltage shut-down hysteresis On state resistance(2) Clamp Voltage Supply current IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C IS=20mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C -IOUT=4A; Tj=150C 0 0 41 46 2(1) 3 0.01 Test Conditions Min. 4.5 Typ. 13 3.5 0.5 50 100 65 52 5(1) 6 3 5 0.7 Max. 36 4.5 Unit V V V m m m V A mA A V
RON Vclamp IS
IL(off) VF
Off state output current(2) Output - VCC diode voltage(2)
(1) PowerMOS leakage included. (2) For each channel
Table 5.
Symbol td(on) td(off)
Switching (VCC=13V)
Parameter Turn-on delay time Turn-off delay time Test Conditions RL=6.5 (see Figure 6) RL=6.5 (see Figure 6) RL=6.5 RL=6.5 RL=6.5 (see Figure 6) RL=6.5 (see Figure 6) Min. Typ. 25 35 see Figure 19 see Figure 20 0.24 0.2 Max. Unit s s V/s V/s mJ mJ
dVOUT/dt(on) Turn-on voltage slope dVOUT/dt(off) Turn-off voltage slope WON WOFF Switching energy losses during twon Switching energy losses during twoff
5/26
Electrical specifications Table 6.
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH VCSD(hyst) VCSCL
VND5050AJ-E / VND5050AK-E
Logic input
Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current CS_DIS hysteresis voltage CS_DIS clamp voltage ICSD=1mA ICSD=-1mA VCSD=2.1V 0.25 5.5 -0.7 7 VCSD=0.9V 1 2.1 10 IIN=1mA IIN=-1mA VIN=2.1V 0.25 5.5 -0.7 0.9 7 VIN=0.9V 1 2.1 10 Test Conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
Table 7.
Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG VON
Protections and Diagnostics (1) Parameter DC Short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp Output voltage drop limitation IOUT=2A; VIN=0; L=6mH IOUT=0.1A; Tj= -40C...+150C (see Figure 7) Test Conditions VCC=13V 5V7 175
TRS + 1 TRS + 5 135
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
6/26
VND5050AJ-E / VND5050AK-E Table 8.
Symbol K0
Electrical specifications
Current Sense (8VParameter IOUT/ISENSE Test Conditions IOUT=0.05A; VSENSE=0.5V;VCSD=0V; Tj= -40C...150C IOUT=1A; VSENSE=0.5V;VCSD=0V; Tj= -40C Tj= 25C...150C IOUT=2A; VSENSE=4V;VCSD=0V; Tj= -40C Tj= 25C...150C IOUT=4A; VSENSE=4V;VCSD=0V; Tj=-40C Tj=25C...150C IOUT=0A; VSENSE=0V; VCSD=5V; VIN=0V; Tj=-40C...150C VCSD=0V; VIN=5V; Tj=-40C...150C IOUT=2A; VSENSE=0V; VCSD=5V; VIN=5V; Tj=-40C...150C Min. Typ. Max. Unit
1270 1470 1570 1740 1790 1880 1900 0 0
2360 2020 2020 2020 2020 2010 2010
3450 2610 2470 2320 2250 2160 2120 1 2 A A
K1
IOUT/ISENSE
K2
IOUT/ISENSE
K3
IOUT/ISENSE
ISENSE0
Analog sense leakage current
0 5
1
A V
VSENSE
Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog sense output current in overtemperature condition
IOUT=4A; VCSD=0V
VSENSEH
VCC=13V; RSENSE=10K
9
V
ISENSEH
VCC=13V; VSENSE=5V
8
mA
Delay Response time tDSENSE1H from falling edge of CS_DIS pin Delay Response time tDSENSE1L from rising edge of CS_DIS pin Delay Response time tDSENSE2H from rising edge of INPUT pin Delay Response time tDSENSE2L from falling edge of INPUT pin
VSENSE<4V, 0.5A50
100
s
5
20
s
80
300
s
100
250
s
7/26
Electrical specifications Figure 4. Current Sense Delay Characteristics
VND5050AJ-E / VND5050AK-E
INPUT CS_DIS LOAD CURRENT SENSE CURRENT
tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L
Figure 5.
IOUT/ISENSE Vs. IOUT (see Table 8 for details)
Iout/Isense
4000 3500 3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5
min Tj=25...150C max Tj=25...150C
max Tj= -40C to 150C
typical value
min Tj=-40C to 150C
Iout (A)
8/26
VND5050AJ-E / VND5050AK-E Table 9. Truth table
INPUT L H L H L H L H H L H L OUTPUT L H L L L L L L L H H L
Electrical specifications
CONDITIONS Normal operation Overtemperature Undervoltage Short circuit to GND (Rsc 10 m) Short circuit to VCC Negative output voltage clamp
SENSE (VCSD=0V)(1) 0 Nominal 0 VSENSEH 0 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
Figure 6.
Switching characteristics
VOUT
tWon
80%
tWoff
90% dVOUT/dt(off)
dVOUT/dt(on) tr 10% tf
t INPUT td(on)
td(off)
t
Figure 7.
Output Voltage Drop Limitation
Vcc-Vout
Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
9/26
Electrical specifications Table 10. Electrical Transient Requirements
TEST LEVELS III -75V +37V -100V +75V -6V +40V IV -100V +50V -150V +100V -7V +40V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse
VND5050AJ-E / VND5050AK-E
ISO 7637-2: 2004(E) Test Pulse 1 2a 3a 3b 4 5b(1) ISO 7637-2: 2004(E) Test Pulse 1 2a 3a 3b 4 5b(1) CLASS C E
Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms
Delays and Impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
TEST LEVEL RESULTS III C C C C C C CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. IV C C C C C C
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/26
VND5050AJ-E / VND5050AK-E Figure 8. Waveforms
NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT
VUSDhyst VUSD
Electrical specifications
SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT
OVERLOAD OPERATION Tj INPUT CS_DIS LOAD CURRENT SENSE CURRENT
ILIMH ILIML VSENSEH TR TTSD TRS
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
11/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
2.4
Figure 9.
Iloff (uA)
1 0.875 0.75 0.625 0.5 0.375 0.25
Electrical characteristics curves
Off State Output Current Figure 10. High Level Input Current
Iih (uA)
5 4.5
Off State Vcc=13V Vin=Vout=0V
4 3.5 3 2.5 2 1.5 1
Vin=2.1V
0.125 0 -50 -25 0 25 50 75 100 125 150 175
0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 11. Input Clamp Voltage
Vicl (V)
7 6.8 6.6 6.4 6.2 6 5.8 5.6
Figure 12. Input High Level
Vih (V)
4 3.5 3 2.5 2 1.5 1
Iin=1mA
5.4 5.2 5 -50 -25 0 25 50 75 100 125 150 175 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 13. Input Low Level
Vil (V)
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Figure 14. Input Hysteresis Voltage
Vhyst (V)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
12/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 15. On State Resistance Vs. Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175
Figure 16. On State Resistance Vs. VCC
Ron (mOhm)
100 90
Iout=2A Vcc=13V
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25
Tc= 150C
Tc= 125C
Tc= 25C
Tc= - 40C
30
35
40
Tc (C)
Vcc (V)
Figure 17. Undervoltage Shutdown
Vusd (V)
16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Figure 18. ILIMH Vs. Tcase
Ilimh (A)
25 22.5
Vcc=13V
20 17.5 15 12.5 10 7.5 5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 19. Turn-on Voltage Slope
(dVout/dt)on (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 20. Turn-off Voltage Slope
(dVout/dt)off (V/ms)
1000 900
Vcc=13V RI=6.5Ohm
800 700 600 500 400 300 200 100 0 -50 -25
Vcc=13V RI=6.5Ohm
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
13/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
Figure 21. STAT_DIS Clamp Voltage
Vsdcl(V)
14
Figure 22. Low Level STAT_DIS Voltage
Vsdl(V)
8 7
12
Isd=1mA
10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 23. High Level STAT_DIS Voltage
Vsdh(V)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
14/26
VND5050AJ-E / VND5050AK-E
Application information
3
Application information
Figure 24. Application schematic
+5V
VCC Rprot CS_DIS Dld C Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE CEXT VGND RGND DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
3.1.1
GND protection network against reverse battery
Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND.
15/26
Application information
VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
C I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k. Recommended values: Rprot =10k, CEXT=10nF.
16/26
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4
4.1
Package and PCB thermal data
PowerSSO-12 thermal data
Figure 25. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 26. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/W)
70 65 60 55 50 45 40 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
Figure 27. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
Footprint 2 cm2 8 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Pulse Calculation Formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T
17/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 28. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.7 2.8 7 10 22 26 0.001 0.0025 0.05 0.2 0.27 3 0.1 0.8 6 0.1 1 9 10 15 20 9 10 15 2 8
18/26
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4.2
PowerSSO-24 thermal data
Figure 29. PowerSSO-24 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 30. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/W)
55 50 45 40 35 30 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
Figure 31. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
Footprint 2 cm2 8 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Pulse Calculation Formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T
19/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 32. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.4 2 6 7.7 9 28 0.001 0.0022 0.025 0.75 1 2.2 4 5 9 17 9 17 8 10 2 8
20/26
VND5050AJ-E / VND5050AK-E
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 33. PowerSSO-12TM Package Dimensions
D h x 45 C A2 B ddd 12 C 7 A 0.25 mm GAUGE PLANE
SEATING PLANE
C A1 L K
X E H
Y 1 e 6
BOTTOM VIEW
Table 11.
PowerSSO-12TM Mechanical Data
millimeters Min 1.250 0.000 1.100 0.230 0.190 4.800 3.800 5.800 0.250 0.400 0 1.900 3.600 Typ Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000 6.200 0.500 1.270 8 2.500 4.200 0.100
Symbol A A1 A2 B C D E e H h L k X Y ddd
0.800
21/26
Package information Figure 34. PowerSSO-24TM Package Dimensions
VND5050AJ-E / VND5050AK-E
Table 12.
PowerSSO-24TM Mechanical Data
millimeters Min 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.1 0.06 10.1 0.55 4.1 6.5 10.5 0.4 0.85 10deg 4.7 7.1 Typ Max 2.47 2.40 0.075 0.51 0.32 10.50 7.6
Symbol A A2 a1 b c D E e e3 G G1 H h L N X Y
22/26
VND5050AJ-E / VND5050AK-E
Package information
5.2
Packing information
Figure 35. PowerSSO-12 Tube Shipment (No Suffix)
B C
A
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm.
100 2000 532 1.85 6.75 0.6
Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
23/26
Package information Figure 37. PowerSSO-24 Tube Shipment (No Suffix)
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
VND5050AJ-E / VND5050AK-E
C
B
49 1225 532 3.5 13.8 0.6
A
All dimensions are in mm.
Figure 38. PowerSSO-24 Tape And Reel Shipment (Suffix "TR")
REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W Tape Hole Spacing P0 ( 0.1) Component Spacing P Hole Diameter D ( 0.05) Hole Diameter D1 (min) Hole Position F ( 0.1) Compartment Depth K (max) Hole Spacing P1 ( 0.1)
All dimensions are in mm.
24 4 12 1.55 1.5 11.5 2.85 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
24/26
VND5050AJ-E / VND5050AK-E
Revision history
6
Revision history
Table 13.
Date 30-Mar-2006 14-Apr-2006
Document revision history
Revision 1 2 Initial release. PowerSSO-24 dimensions table update. Changes
25/26
VND5050AJ-E / VND5050AK-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
26/26

▲Up To Search▲

Price & Availability of VND5050AJTR-E

	To Download VND5050AJTR-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .